Cmu_Freeze - Freeze Register - Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

11.5.42 CMU_FREEZE - Freeze Register

Offset
0x144
Reset
Access
Name
Bit Name
31:1 Reserved
0 REGFREEZE
When set, the update of the Low Frequency clock control registers is postponed until this bit is cleared. Use this bit to up-
date several registers simultaneously.
Value
0
1
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Reset Access Description
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0 RW Register Update Freeze
Mode Description
UPDATE Each write access to a Low Frequency clock control register is updated
into the Low Frequency domain as soon as possible.
FREEZE The LE Clock Control registers are not updated with the new written
value.
Bit Position
Reference Manual
CMU - Clock Management Unit
1.2 Conven-
Rev. 1.1 | 357