Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual page 49

4.2.5.2.1 WS0 Mode
In general, when accessing a peripheral, the latency in number of HFCLK cycles, not including master arbitration, is given by:
where N is the throughput of the slave's bus interface in number of PERCLK cycles per transfer, including any wait cycles
slave cycles
Note that a latency of 1 cycle corresponds to 0 wait states.
Additionally, for back-to-back accesses to the same peripheral, the throughput in number of cycles per transfer is given by:
Lastly, in the highest performing case, where PERCLK equals HFCLK and the slave does not introduce any additional wait states, the
access latency in number of cycles is given by:
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N = N
bus cycles slave cycles
N = N ∙ f
bus cycles slave cycles
N = (N + 1) ∙ f
bus cycles slave cycles
N = (N + 1) ∙ f
bus cycles slave cycles
introduced by the slave.
Figure 4.4. Bus Access Latency (General Case)
N = N
bus cycles slave cycles
N = (N
bus cycles slave cycles
Figure 4.5. Bus Access Throughput (Back-to-Back Transfers)
N
bus cycles
N
bus cycles
Figure 4.6. Bus Access Latency (Max Performance)
∙ f /f , best-case write accesses
HFCLK PERCLK
/f + 1, best-case read accesses
HFCLK PERCLK
/f - 1, worst-case write accesses
HFCLK PERCLK
/f , worst-case read accesses
HFCLK PERCLK
∙ f /f , write accesses
HFCLK PERCLK
+ 1) ∙ f /f , read accesses
HFCLK PERCLK
= 1, write accesses
= 2, read accesses
Reference Manual
Memory and Bus System
Rev. 1.1 | 49