Block Diagrams - Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

2.2 Block Diagrams

The block diagram for the EFR32 System-On-Chip series is shown in
29).
Core / Memory
ARM Cortex TM M4 processor
with DSP extensions, FPU and MPU
Debug Interface RAM Memory
Radio Transceiver
RFSENSE
Sub GHz
I
LNA
RF Frontend
PA
Q
To Sub GHz
receive I/Q
RFSENSE
mixers and PA
2.4 GHz
I
LNA
RF Frontend
BALUN
PA
To 2.4 GHz receive
Q
I/Q mixers and PA
Lowest power mode with peripheral operational:
EM0—Active
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Flash Program
Memory
LDMA Controller
DEMOD
IFADC
PGA
AGC
Frequency
MOD
Synthesizer
To Sub GHz
and 2.4 GHz PA
EM1—Sleep EM2—Deep Sleep
Figure 2.1. EFR32 System-On-Chip Block Diagram
(Figure 2.1 EFR32 System-On-Chip Block Diagram on page
Clock Management
H-F Crystal H-F
Oscillator RC Oscillator
Auxiliary H-F RC L-F
RC Oscillator
Oscillator
L-F Crystal
Ultra L-F RC
Oscillator
Oscillator
32-bit bus
Peripheral Reflex System
Serial I/O Ports
Interfaces
External
USART
Interrupts
Low Energy General
UART TM Purpose I/O
2
I C Pin Reset
Pin Wakeup
EM3—Stop
System Overview
Energy Management
Voltage
Voltage Monitor
Regulator
DC-DC
Power-On Reset
Converter
Number Generator
Brown-Out
Detector
Timers and Triggers
Timer/Counter Protocol Timer
Low Energy Low Energy
Timer Sensor Interface
Pulse Counter Watchdog Timer
Real Time
Counter and Cryotimer
Calendar
EM4—Hibernate
Reference Manual
Other
CRYPTO
CRC
True Random
SMU
Analog I/F
ADC
Analog
Comparator
IDAC
VDAC
Op-Amp
EM4—Shutoff
Rev. 1.1 | 29