Introduction - Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

4.1 Introduction

The EFR32 contains an AMBA AHB Bus system to allow bus masters to access the memory mapped address space. A multilayer AHB
bus matrix connects the 5 master bus interfaces to the AHB slaves
lows several AHB slaves to be accessed simultaneously. An AMBA APB interface is used for the peripherals, which are accessed
through an AHB-to-APB bridge connected to the AHB bus matrix. The 5 AHB bus masters are:
• Cortex-M4 ICode: Used for instruction fetches from Code memory (valid address range: 0x00000000 - 0x1FFFFFFF)
• Cortex-M4 DCode: Used for debug and data access to Code memory (valid address range: 0x00000000 - 0x1FFFFFFF)
• Cortex-M4 System: Used for data and debug access to system space. It can access entire memory space except Code memory
(valid address range: 0x20000000 - 0xFFFFFFFF)
• DMA: Can access the entire memory space except the internal core memory region and the DMEM code region
• Sequencer Code: Used for instruction fetches and data accesses. Instruction fetches still come from data memory. (valid address
range: 0x00000000 - 0x0FFFFFFF, 0x20000000 - 0x3FFFFFFF)
• Sequencer System: Can access entire memory space except internal core memory region and RAM code space (valid address
range: 0x00000000 - 0x0FFFFFFF, 0x20000000 - 0xDFFFFFFF)
• BUFC: Can access general purpose SRAM (valid address range: 0x20000000 - 0x20FFFFFF)
• FRC: Can access general purpose SRAM (valid address range: 0x20000000 - 0x20FFFFFF)
Cortex-M
Sequencer
BUFC
FRC
DMA
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(Figure 4.1 EFR32 Bus System on page
ICode
AHB Multilayer
Bus Matrix
DCode
System
Code
System
Figure 4.1. EFR32 Bus System
Memory and Bus System
Flash
RAM0
RAMn
SEQ_RAM
CRYPTO
Peripheral 0
AHB/APB
Bridge
Peripheral n
Reference Manual
42). The bus matrix al-
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