Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual page 53

4.3.1.1 Delayed Synchronization
After writing data to a register which value is to be synchronized into the Low Energy Peripheral using delayed synchronization, a corre-
sponding busy flag in the <module_name>_SYNCBUSY register (e.g. LETIMER_SYNCBUSY) is set. This flag is set as long as syn-
chronization is in progress and is cleared upon completion.
Note: Subsequent writes to the same register before the corresponding busy flag is cleared is not supported. Write before the busy flag
is cleared may result in undefined behavior. In general the SYNCBUSY register only needs to be observed if there is a risk of multiple
write access to a register (which must be prevented). It is not required to wait until the relevant flag in the SYNCBUSY register is
cleared after writing a register. E.g., EM2 Deep Sleep can be entered directly after writing a register.
See Figure 4.12 Write Operation to Low Energy Peripherals on page 53
High Frequency Clock Domain
Write request 0
Write request 1
Write request n
Write request [0:n]
Set 0
Set 1
Set n
4.3.1.2 Immediate Synchronization
In contrast to the peripherals with delayed synchronization, peripherals with immediate synchronization do not experience a delay from
a value is written to it takes effect in the peripheral. They are updated immediately on the peripheral write access. If such a write is done
close to an edge on the clock of the peripheral, the write is delayed to after the clock edge. This will introduce wait-states on the periph-
eral access.
Peripherals with immediate synchronization each have a SYNCBUSY register. Commands written to a peripheral with immediate syn-
chronization are not executed before the first peripheral clock after the write. In this period, the SYNCBUSY flag for the command regis-
ter is set, indicating that the command has not yet been performed. Secondly, to maintain compatibility with the Gecko series, the rest
of the SYNCBUSY registers are also present, but these are always 0, indicating that register writes are always safe.
Note: If compatibility with the Gecko series is a requirement for a given application, the rules that apply to delayed synchronization with
respect to SYNCBUSY should also be followed for the peripherals that support immediate synchronization.
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High Frequency Clock
Register 0
Register 1
.
.
.
Register n
Clear 0
Syncbusy Register 0
Clear 1
Syncbusy Register 1
.
.
.
Clear n
Syncbusy Register n
Figure 4.12. Write Operation to Low Energy Peripherals
for an overview of the writing mechanism operation.
Low Frequency Clock Domain
Freeze
Low Frequency Clock
Synchronizer 0
Synchronizer 1
.
.
.
Synchronizer n
Synchronization Done
Reference Manual
Memory and Bus System
Low Frequency Clock
Register 0 Sync
Register 1 Sync
.
.
.
Register n Sync
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