Reset Control/Status Register (Rstcsr) - Hitachi SH7032 Hardware Manual

• Bits 4 and 3 (Reserved): These bits are always read as 1. The write value should always be 1.
• Bits 2–0 (Clock Select 2–0 (CKS2–CKS0)): CKS2–CKS0 select one of eight internal clock
sources for input to TCNT. The clock signals are obtained by dividing the frequency of the
system clock (φ).
Bit 2: CKS2 Bit 1: CKS1 Bit 0: CKS0 Clock Source
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
Note: * The overflow interval listed is the time from when the TCNT begins counting at H'00 until an
overflow occurs.
12.2.3

Reset Control/Status Register (RSTCSR)

RSTCSR is an eight-bit read/write register that controls output of the reset signal generated by
timer counter (TCNT) overflow and selects the internal reset signal type. RSTCSR differs from
other registers in that it is more difficult to write. See section 12.2.4, Notes on Register Access, for
details. RSTCR is initialized to H'1F by input of a reset signal from the RES pin, but is not
initialized by the internal reset signal generated by overflow of the WDT. It is initialized to H'1F
in standby mode.
Bit:
Bit name:
Initial value:
R/W:
Note: * Only 0 can be written in bit 7, to clear the flag.
φ/2 (Initial value)
0
φ/64
1
φ/128
0
φ/256
1
φ/512
0
φ/1024
1
φ/4096
0
φ/8192
1
7 6
WOVF RSTE RSTS
0 0
R/(W)* R/W R/W
Description
Overflow Interval * (φ = 20 MHz)
25.6 µs
819.2 µs
1.6 ms
3.3 ms
6.6 ms
13.1 ms
52.4 ms
104.9 ms
5 4 3
— —
0 1 1
— —
2 1 0
— — —
1 1 1
— — —
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