Hitachi SH7032 Hardware Manual page 682

Table B.1 Pin State In Resets, Power-Down State, and Bus-Released State (cont)
Category
Serial communication
interface (SCI)
A/D converter
I/O ports
—: One of the multiplexed pin functions is allocated, but the pin functions in the reset state are
different.
I: Input
O: Output
H: High
L: Low
Z: High impedance
K: Input pins are high-impedance, output pins hold their state.
Notes: *1 When the port high impedance bit (HIZ) in the standby control register (SBYCR) is set
to 1, the output pins become high-impedance.
*2 When the pin pull-up control bit (WPU) in the wait state control register (WCR3) is set to
1, the WAIT pin is pulled up, but if set to 0, it is not pulled up.
Pin
TxD0–TxD1
RxD0,RxD1
SCK0,SCK1
AN7–AN0
ADTRG
PA14, PA12,
PA7–PA0
PA15, PA13,
PA11–PA8,
PB15–PB0
PC7–PC0
Reset
Power-On Manual Standby Sleep Released
— Z
— I
— I
Z Z
— I
— I/O
Z I/O
Z I
Pin State
Power-Down
1
K *
O
Z I
Z I/O
Z I
Z I
1
K *
I/O
1
K *
I/O
Z I
Bus
O
I
I/O
I
I
I/O
I/O
I
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