Timer I/O Control Register (Tior) - Hitachi SH7032 Hardware Manual

Bit 2: Bit 1: Bit 0:
TPSC2 TPSC1 TPSC0
0 0 0
1
1 0
1
1 0 0
1
1 0
1

10.2.10 Timer I/O Control Register (TIOR)

The timer I/O control register (TIOR) is an eight-bit read/write register that selects the output
compare or input capture function for general registers GRA and GRB. It also selects the function
of the TIOCA and TIOCB pins. If output compare is selected, TIOR also selects the output
settings. If input capture is selected, TIOR also selects the input capture edge. TIOR is initialized
to H'88 or H'08 by a reset and in standby mode. Each ITU channel has one TIOR.
Table 10.8 Timer I/O Control Register (TIOR)
Abbrevi-
Channel ation
0 TIOR0
1 TIOR1
2 TIOR2
3 TIOR3
4 TIOR4
Bit:
Bit name:
Initial value:
R/W:
Note: * Undefined
• Bit 7 (Reserved): Bit 7 is read as undefined. The write value should be 0 or 1.
244
Counter Clock (and Cycle when φ = 10 MHz)
Internal clock φ
Internal clock φ/2
Internal clock φ/4
Internal clock φ/8
External clock A (TCLKA)
External clock B (TCLKB)
External clock C (TCLKC)
External clock D (TCLKD)
Function
TIOR controls the GRs. Some functions vary during PWM. When
channels 3 and 4 are set for complementary PWM mode/reset-
synchronized PWM mode, TIOR3 and TIOR4 settings are not valid.
7 6 5
— IOB2 IOB1
* 0 0
— R/W R/W
4 3
IOB0 — IOA2
0 1
R/W — R/W
(Initial value)
2 1 0
IOA1 IOA0
0 0 0
R/W R/W