Hitachi SH7032 Hardware Manual page 154

• Bits 15–8 (Reserved): These bits are always read as 0.
• Bit 7 (Compare Match Flag (CMF)): Indicates whether the values of RTCNT and the refresh
time constant register (RTCOR) match. When 0, the value of RTCNT and RTCOR do not
match; when 1, the value of RTCNT and RTCOR match.
Bit 7: CMF Description
0 RTCNT value does not equal RTCOR value
To clear CMF, the CPU must read CMF after it has been set to 1, then write a 0
in this bit
1 RTCNT value is equal to RTCOR value
• Bit 6 (Compare Match Interrupt Enable (CMIE)): Enables or disables the compare match
interrupt (CMI) generated when CMF is set to 1 in RTCSR (RTCNT value = RTCOR value).
When cleared to 0, the CMI interrupt is disabled; when set to 1, it is enabled.
Bit 6: CMIE
0
1
• Bits 5–3 (Clock Select Bits 2–0 (CKS2–CKS0)): These bits select the clock input to RTCNT
from among the seven types of clocks created by dividing the system clock (φ). When the input
clock is selected with the CKS2–CKS0 bits, RTCNT starts to increment.
Bit 5: CKS2 Bit 4: CKS1
0 0
1
1 0
1
• Bits 2–0 (Reserved): These bits are always read as 0. The write value should always be 0.
Description
Compare match interrupt request (CMI) is disabled
Compare match interrupt request (CMI) is enabled
Bit 3: CKS0
0
1
0
1
0
1
0
1
Description
Clock input disabled
φ/2
φ/8
φ/32
φ/128
φ/512
φ/2048
φ/4096
(Initial value)
(Initial value)
(Initial value)
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