Refresh Timer Control/Status Register (Rtcsr) - Hitachi SH7032 Hardware Manual

Bit 6: RMODE
0
1
• Bits 5 and 4—CBR Refresh Wait State Insertion Bits 1 and 0 (RLW1, RLW0): These bits
select the number of wait states to be inserted (1–4) during CAS-before-RAS refreshing. When
CBR refresh is performed and the RW1 bit in WCR1 is set to 1, the number of wait states
selected by RLW1 and RLW0 is inserted regardless of the WAIT signal. When the RW1 bit is
cleared to 0, the RLW1 and RLW0 bit settings are ignored and no wait states are inserted.
Bit 5: RLW1
0
1
• Bits 3–0 (Reserved): These bits are always read as 0. The write value should always be 0.
8.2.7

Refresh Timer Control/Status Register (RTCSR)

The refresh timer control/status register (RTCSR) is a 16-bit read/write register that selects the
clock input to the refresh timer counter (RTCNT) and controls compare match interrupts (CMI). It
is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in standby
mode.
To prevent RTCSR from being written incorrectly, it must be written by a different method from
most other registers. A word transfer operation is used, H'A5 is written in the upper byte, and the
actual data is written in the lower byte. For details, see section 8.2.11, Notes on Register Access.
Bit:
Bit name:
Initial value:
R/W:
Bit:
Bit name:
Initial value:
R/W:
118
Description
CAS-before-RAS refresh
Self-refresh
Bit 4: RLW0
0
1
0
1
15 14
— —
0 0
— —
7 6
CMF CMIE CKS2
0 0
R/W R/W
Description
1 state inserted
2 states inserted
3 states inserted
4 states inserted
13 12 11
— — —
0 0
— — —
5 4
CKS1 CKS0
0 0
R/W R/W R/W
10 9
— —
0 0 0
— —
3 2 1
— —
0 0 0
— —
(Initial value)
(Initial value)
8
—
0
—
0
—
0
—