Register Configuration - Hitachi SH7032 Hardware Manual

6.1.3

Register Configuration

The user break controller has five registers as listed in table 6.1. These registers are used for
setting break conditions.
Table 6.1 User Break Controller Registers
Name
Break address register high
Break address register low
Break address mask register high
Break address mask register low
Break bus cycle register
Note: * Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9 are ignored. For details
on the register addresses, see section 8.3.5, Area Descriptions.
Address *
Abbr. R/W
BARH R/W H'5FFFF90
BARL R/W H'5FFFF92
BAMRH R/W H'5FFFF94
BAMRL R/W H'5FFFF96
BBR R/W H'5FFFF98
Initial
Value Bus width
H'0000 8, 16, 32
H'0000 8, 16, 32
H'0000 8, 16, 32
H'0000 8, 16, 32
H'0000 8, 16, 32
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