Hitachi SH7032 Hardware Manual page 538

CK
A21–A0
RAS
CAS
RD(Read)
WRH, WRL,
WR(Read)
AD15–AD0
DPH, DPL
(Read)
DACK0
DACK1
(Read)
RD(Write)
WRH, WRL,
WR(Write)
AD15–AD0
(Write)
DPH, DPL
(Write)
DACK0
DACK1
(Write)
Notes: *1 For t
CAC2
*2 For t
ACC2
*3 For t
RAC2
is measured from A21–A0 or CAS, whichever is negated first.
*4 t
RDH
is measured from A21–A0, RAS, or CAS whichever is negated first.
*5 t
RDH
Figure 20.27 DRAM Bus Cycle: (Long-Pitch, High-Speed Page Mode)
T T
p r
t t
AD AD
Row
t
RASD1
t
RDD
*3
t
RAC2
× (n + 1) – 35 instead of t
, use t
cyc
× (n + 2) – 44 instead of t
, use t
cyc
× (n + 2.5) – 35 instead of t
, use t
cyc
T T
c1 c2
Column
t
CASD2
t
t
RSD
*1
t
CAC2
*2
t
t t
ACC2 RDS
t t
DACD1 DACD2
t t
WSD1 WSD2
t t
WDD1 WDH
t t
WPDD1 WPDH
t t
DACD3 DACD3
× (n + 1) – t
cyc
× (n + 2) – t
cyc
× (n + 2.5) – t
cyc
T T
c1 c2
Column
CASD3
*4
RDH
t t
DACD1 DACD2
t t
WSD1 WSD2
t t
WDD1 WDH
t t
WPDD1 WPDH
t t
DACD3 DACD3
– t .
CASD2 RDS
– t .
AD RDS
– t
RASD2 RDS
t
RASD2
t
CASD3
*5
t
RDH
.
503