Table A.2
16-bit Access Space (In Principle, 8-Bit, 16-Bit and 32-Bit Accessible) (cont)
Address
Register 7
5
H'5FFFF60 SAR2 *
H'5FFFF61
H'5FFFF62
H'5FFFF63
5
H'5FFFF64 DAR2 *
H'5FFFF65
H'5FFFF66
H'5FFFF67
H'5FFFF68 —
H'5FFFF69 —
5
H'5FFFF6A TCR2 *
H'5FFFF6B
H'5FFFF6C —
H'5FFFF6D —
H'5FFFF6E CHCR2
H'5FFFF6F
5
H'5FFFF70 SAR3 *
H'5FFFF71
H'5FFFF72
H'5FFFF73
5
H'5FFFF74 DAR3 *
H'5FFFF75
H'5FFFF76
H'5FFFF77
H'5FFFF78 —
H'5FFFF79 —
5
H'5FFFF7A TCR3 *
H'5FFFF7B
H'5FFFF7C —
H'5FFFF7D —
H'5FFFF7E CHCR3
H5FFFF7F
560
6
5
—
—
—
—
—
—
—
—
—
—
—
—
DM1
DM0
SM1
AM
AL
DS
—
—
—
—
—
—
—
—
—
—
—
—
DM1
DM0
SM1
AM
AL
DS
Bit Name
4
3
2
—
—
—
—
—
—
—
—
—
—
—
—
SM0
RS3
RS2
TM
TS
IE
—
—
—
—
—
—
—
—
—
—
—
—
SM0
RS3
RS2
TM
TS
IE
1
0
Module
DMAC
channel 2
—
—
—
—
—
—
—
—
RS1
RS0
TE
DE
DMAC
channel 3
—
—
—
—
—
—
—
—
RS1
RS0
TE
DE