Hitachi SH7032 Hardware Manual page 32

(10) AC Characteristics Test Conditions.............................................................. 553
20.2.4 A/D Converter Characteristics .............................................................................. 554
Appendix A On-Chip Supporting Module Registers
A.1 List of Registers.................................................................................................................. 555
A.2 Register Tables ................................................................................................................... 565
A.2.1 Serial Mode Register (SMR) SCI.......................................................................... 565
A.2.2 Bit Rate Register (BRR) SCI ................................................................................ 566
A.2.3 Serial Control Register (SCR) SCI........................................................................ 566
A.2.4 Transmit Data Register (TDR) SCI ...................................................................... 568
A.2.5 Serial Status Register (SSR) SCI .......................................................................... 568
A.2.6 Receive Data Register (RDR) SCI........................................................................ 570
A.2.7 A/D Data Register AH-DL (ADDRAH-ADDRL) A/D ...................................... 571
A.2.8 A/D Control/Status Register (ADCSR) A/D ........................................................ 571
A.2.9 A/D Control Register (ADCR) A/D...................................................................... 573
A.2.10 Timer Start Register (TSTR) ITU ......................................................................... 573
A.2.11 Timer Synchronization Register (TSNC) ITU...................................................... 574
A.2.12 Timer Mode Register (TMDR) ITU...................................................................... 576
A.2.13 Timer Function Control Register (TFCR) ITU ..................................................... 577
A.2.14 Timer Control Registers 0-4 (TCR0-TCR4) ITU ................................................ 578
A.2.15 Timer I/O Control Registers 0-4 (TIOR0-TIOR4) ITU....................................... 579
A.2.16 Timer Interrupt Enable Registers 0-4 (TIER0-TIER4) ITU................................ 580
A.2.17 Timer Status Registers 0-4 (TSR0-TSR4) ITU ................................................... 581
A.2.18 Timer Counter 0-4 (TCNT0-TCNT4) ITU.......................................................... 582
A.2.19 General Registers A0-4 (GRA0-GRA4) ITU ...................................................... 583
A.2.20 General Registers B0-4 (GRB0-GRB4) ITU ....................................................... 584
A.2.21 Buffer Registers A3, 4 (BRA3, BRA4) ITU......................................................... 585
A.2.22 Buffer Registers B3, 4 (BRB3, BRB4) ITU.......................................................... 586
A.2.23 Timer Output Control Register (TOCR) ITU ....................................................... 587
A.2.24 DMA Source Address Registers 0-3 (SAR0-SAR3) DMAC .............................. 588
A.2.25 DMA Destination Address Registers 0-3 (DAR0-DAR3) DMAC...................... 589
A.2.26 DMA Transfer Count Registers 0-3 (TCR0-TCR3) DMAC ............................... 590
A.2.27 DMA Channel Control Registers 0-3 (CHCR0-CHCR3) DMAC ...................... 591
A.2.28 DMA Operation Registers (DMAOR) DMAC ..................................................... 594
A.2.29 Interrupt Priority Setting Register A (IPRA) INTC.............................................. 595
A.2.30 Interrupt Priority Setting Register B (IPRB) INTC .............................................. 596
A.2.31 Interrupt Priority Setting Register C (IPRC) INTC .............................................. 597
A.2.32 Interrupt Priority Setting Register D (IPRD) INTC.............................................. 598
A.2.33 Interrupt Priority Setting Register E (IPRE) INTC ............................................... 599
A.2.34 Interrupt Control Register (ICR) INTC ................................................................ 600
A.2.35 Break Address Register H (BARH) UBC ............................................................. 601
A.2.36 Break Address Register L (BARL) UBC.............................................................. 602
A.2.37 Break Address Mask Register H (BAMRH) UBC................................................ 603
................................................. 555
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