Hitachi SH7032 Hardware Manual page 253

Especially, if, as shown in figure 9.26, the DMA bus cycle is a full access to DRAM or if a
refresh request is generated, sampling of DREQ takes place before DACK is output as
mentioned above. This phenomenon is found when one of the following transfers is made with
DREQ set to level detection in DMA cycle-steal mode, in a system which employs DRAM
(refresh enabled).
CK
Tp Tr
DACK
Sampling point
DRAM bus cycle
(Full access)
Figure 9.26 Example of DREQ Sampling before Output of DACK
• Transfer from a device with DACK to memory in single address mode (not restricted to
DRAM)
• Transfer from DRAM to a device with DACK in single address mode
• Output at DACK write in dual address mode
• Output at DACK read in dual address mode and DMA transfer using DRAM as the source
Remedy:
To prevent unnecessary DMA transfers, configure the system so that DREQ is edge-detected
and the edge corresponding to the next transfer request occurs after DACK output.
8. When the following operations are performed in the order shown when the pin to which DREQ
input is assigned is designated as a general input pin by the pin function controller (PFC) and
inputs a low-level signal, the DREQ falling edge is detected, and a DMA transfer request
accepted, immediately after the setting in (b) is performed:
(a) A channel control register (CHCRn) setting is made so that an interrupt is detected at the
falling edge of DREQ.
(b) The function of the pin to which DREQ input is assigned is switched from general input to
DREQ input by a pin function controller (PFC) setting.
Therefore, when switching the pin function from general input pin to DREQ input, the pin
function controller (PFC) setting should be changed to DREQ input while the pin to which
DREQ input is assigned is high.
218
Tc Refresh
Sampling point
When refresh operation is entered
Sampling point of DREQ for DACK output position
differs with presence/absence of the refresh operation.
T1 T2