General Registers A And B (Gra And Grb) - Hitachi SH7032 Hardware Manual

10.2.7

General Registers A and B (GRA and GRB)

Each of the five ITU channels has two 16-bit general registers (GR) for a total of ten registers.
Each GR is a 16-bit read/write register that can function as either an output compare register or an
input capture register. The function is selected by settings in the timer I/O control register (TIOR).
When a general register (GRA/GRB) is used as an output compare register, its value is constantly
compared with the timer counter (TCNT) value. When the two values match (compare match), the
IMFA/IMFB bit is set to 1 in the timer status register (TSR). If compare match output is selected
in TIOR, a specified value is output at the output compare pin.
When a general register is used as an input capture register, an external input capture signal is
detected and the TCNT value is stored. The IMFA/IMFB bit in the corresponding TSR is set to 1
at the same time. The valid edge or edges of the input capture signal are selected in TIOR. The
TIOR setting is ignored when set for PWM mode, complementary PWM mode, or reset-
synchronized PWM mode.
General registers are connected to the CPU by a 16-bit bus, so general registers can be written or
read by either word access or byte access. General registers are initialized as output compare
registers (no pin output) by a reset and in standby mode. The initial value is H'FFFF.
Table 10.5 General Registers A and B (GRA and GRB)
Channel Abbreviation Function
0 GRA0, GRB0 Output compare/input capture dual register
1 GRA1, GRB1
2 GRA2, GRB2
3 GRA3, GRB3 Output compare/input capture dual register. Can also be set for buffer
GRA4, GRB4 operation in combination with the buffer registers (BRA, BRB)
4
Bit:
Bit name:
Initial value:
R/W:
Bit:
Bit name:
Initial value:
R/W:
240
15 14 13
1 1
R/W R/W R/W
7 6
1 1
R/W R/W R/W
12 11
1 1 1
R/W R/W
5 4 3
1 1 1
R/W R/W
10 9
1 1
R/W R/W R/W
2 1
1 1
R/W R/W R/W
8
1
0
1