Wait State Control; Byte Access Control - Hitachi SH7032 Hardware Manual

A high-level duty of 35% or 50% can be selected for the RD signal using the RD duty bit
(RDDTY) in BCR. When RDDTY is 1, the high-level duty is 35% of the T3 or T w state,
lengthening the access time for external devices.
8.6.2

Wait State Control

When the address/data multiplexed I/O space is accessed, the WAIT pin input signal is sampled
and a wait state inserted whenever a low level is detected, regardless of the WCR setting. Figure
8.33 shows an example in which a WAIT signal causes one wait state to be inserted.
CK
A21–A0
CS
AH
RD
Read
AD15–AD0
WRH, WRL
Write
AD15–AD0
WAIT
Figure 8.33 Wait State Timing For Address/Data Multiplexed I/O Space Access
8.6.3

Byte Access Control

The byte access control signals when the address/data multiplexed I/O space is being accessed are
of two types (WRH, WRL, A0, or WR, HBS, LBS), just as for byte access control of external
160
T1 T2
Address
Address
Tw
(wait state)
T3
Data (input)
Data (output)
T4