Hitachi SH7032 Hardware Manual page 352

Bit:
Bit name:
Initial value:
R/W:
Different Triggers for TPC Output Groups 3 and 2: If TPC output groups 3 and 2 are triggered
by different compare matches, the address of the upper 4 bits of NDRB (group 3) is H'5FFFFF4
and the address of the lower 4 bits of NDRB (group 2) is H'5FFFFF6. Bits 3–0 of address
H'5FFFFF4 and bits 7–4 of address H'5FFFFF6 are reserved bits. These bits are always read as 1.
The write value should always be 1.
Address H'5FFFFF4:
• Bits 7–4 (Next Data 15–12 (NDR15–NDR12)): NDR15–NDR12 store the next output data for
TPC output group 3.
• Bits 3–0 (Reserved): These bits are always read as 1. The write value should always be 1.
Bit:
Bit name:
Initial value:
R/W:
Address H'5FFFFF6:
• Bits 7–4 (Reserved): These bits are always read as 1. The write value should always be 1.
• Bits 3–0 (Next Data 11–8 (NDR11–NDR8)): NDR11–NDR8 store the next output data for
TPC output group 2.
Bit:
Bit name:
Initial value:
R/W:
7 6
— —
1 1
— —
7 6
NDR15 NDR14 NDR13
0 0
R/W R/W
7 6
— —
1 1
— —
5 4
— — —
1 1
— — —
5 4
NDR12 —
0 0
R/W R/W —
5 4
— — NDR11
1 1
— — R/W
3 2 1
— —
1 1 1
— —
3 2 1
— —
1 1 1
— —
3 2 1
NDR10 NDR9
0 0 0
R/W R/W
0
—
1
—
0
—
1
—
0
NDR8
0
R/W
317