Input Sampling Time And A/D Conversion Time - Hitachi SH7032 Hardware Manual

14.4.3

Input Sampling Time and A/D Conversion Time

With a built-in sample-and-hold circuit, the A/D converter performs input sampling at time t
after control/status register (ADSCR) access is started. See figure 14.5 for A/D conversion timing
and table 14.4 for A/D conversion times.
The total conversion time includes t
purpose of t is to synchronize the ADCSR write time with the A/D conversion process; therefore
D
the duration of t is variable. As a result, the total conversion time varies within the ranges shown
D
in table 14.4.
In scan mode, the ranges given in table 14.4 apply to the first conversion. The duration of the
second and subsequent conversion processes is fixed at 256 states (CKS = 0) or 128 states (CKS =
1).
Address
Input sampling
t A/D start delay
D
t Input sampling time
SPL
t A/D conversion time
CONV
Notes: *1 ADSCR write cycle
*2 ADSCR address
420
and the input sampling time, as shown in figure 14.5. The
D
*1
CK
*2
Write
signal
timing
ADF
t
D
Figure 14.5 A/D Conversion Timing
t
SPL
t
CONV
D