Hitachi SH7032 Hardware Manual page 147

Table 8.5 Single-Mode DMA Memory Read Cycle States (External Memory Space)
WAIT Pin Input
Bits 15–8:
DRW7–DRW0 Signal
0 Not sampled during
single-mode DMA
memory read cycle *
1 Sampled during
single-mode DMA
memory read cycle
(Initial value)
Note: * Sampled in the address/data multiplexed I/O space.
• Bits 7–0 (Single-Mode DMA Memory Write Wait State Control (DWW7–DWW0)): DWW7–
DWW0 determine the number of states in single-mode DMA memory write cycles for each
area and whether or not to sample the WAIT signal. Bits DWW7–DWW0 correspond to areas
7–0, respectively. If a bit is cleared to 0, the WAIT signal is not sampled during the single-
mode DMA memory write cycle for the corresponding area. If it is set to 1, sampling takes
place.
The number of states for areas accesses based on bit settings is the same as indicated for
single-mode DMA memory read cycles. See bits 15–8, Wait State Control During Single-
Mode DMA Memory Transfer (DRW7–DRW0), for details.
Table 8.6 summarizes single-mode DMA memory write cycle state information.
112
Single-Mode DMA Memory Read Cycle States
(External Memory Space)
External Memory Space
Areas 1, 3–5,7: 1 state,
fixed
Areas 0, 2, 6: 1 state +
long wait state
Areas 1, 3–5, 7: 2 states
+ wait states from WAIT
Areas 0, 2, 6: 1 state +
long wait state + wait
state from WAIT
Multiplexed
DRAM Space I/O
Column address 4 states +
cycle: 1 state, wait states
from WAIT
fixed (short pitch)
Column address
cycle: 2 states +
wait state from
WAIT (long pitch)