Hitachi SH7032 Hardware Manual page 539

CK
A21–A0
RAS
CAS
RD(Read)
WRH, WRL,
WR(Read)
AD15–AD0
DPH, DPL
(Read)
DACK0
DACK1
(Read)
RD(Write)
WRH, WRL,
WR(Write)
AD15–AD0
(Write)
DPH, DPL
(Write)
DACK0
DACK1
(Write)
WAIT
Notes: *1 For t
CAC2
*2 For t
ACC2
*3 For t
RAC2
Figure 20.28 DRAM Bus Cycle: (Long-Pitch, High-Speed Page Mode + Wait State)
504
T T
p r
Row
× (n + 1) – 35 instead of t
, use t
cyc
× (n + 2) – 44 instead of t
, use t
cyc
× (n + 2.5) – 35 instead of t
, use t
cyc
T T
c1 w
Column
t
RDD
*1
t
CAC2
*2
t
ACC2
*3
t
RAC2
t t t
WTS WTH WTS
× (n + 1) – t
cyc CASD2
× (n + 2) – t
cyc AD
× (n + 2.5) – t
cyc
T
c2
t
RSD
t
WTH
– t .
RDS
– t .
RDS
– t .
RASD1 RDS