Hitachi SH7032 Hardware Manual page 602

Table A.5 SCR Bit Functions
Bit Bit Name
7 Transmit interrupt
enable (TIE)
6 Receive interrupt
enable (RIE)
5 Transmit enable (TE) 0
4 Receive enable (RE) 0
3 Multiprocessor inter-
rupt enable (MPIE)
2 Transmit end inter-
rupt enable (TEIE)
1 Clock enable 1
(CKE1)
0 Clock enable 0
(CKE0)
Value Description
0 Transmit data-empty interrupt request (TXI) disabled
1 Transmit data-empty interrupt request (TXI) enabled
0 Receive-data-full interrupt request (RXI) and receive-error
interrupt request (ERI) disabled
1 Receive-data-full interrupt request (RXI) and receive-error
interrupt request (ERI)
Transmission disabled
1 Transmission enabled
Reception disabled
1 Reception enabled
0 Multiprocessor interrupts disabled (normal receive operation)
Clear conditions: (1) MPIE bit cleared to zero; (2) When data
the MPB = 1 is received
1 Multiprocessor interrupts enabled. Disables receive interrupts
(RXI), receive error interrupts (ERI), and setting of RDRF,
FER, and ORER flags in SSR until data with a "1"
multiprocessor bit is received
0 Transmit interrupt requests (TEI) disabled
1 Transmit interrupt requests (TEI) enabled
0 0 Asynchronous
mode
Synchronous
mode
0 1 Asynchronous
mode
Synchronous
mode
1 0 Asynchronous
mode
Synchronous
mode
1 1 Asynchronous
mode
Synchronous
mode
Internal clock/SCK pin is input pin (input
signal ignored) or output pin (output level
undetermined)
Internal clock/SCK pin is synchronous
clock output
Internal clock/SCK pin is clock output
Internal clock/SCK pin is serial clock
output
External clock/SCK pin is clock input
External clock/SCK pin is serial clock
input
External clock/SCK pin is clock input
External clock/SCK pin is serial clock
input
(Initial value)
(Initial value)
(Initial value)
(Initial value)
(Initial value)
(Initial value)
(Initial value)
(Initial value)
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