Hitachi SH7032 Hardware Manual page 244

CK
DREQ
Bus cycle
CPU
DACK
Note: When DREQ is negated at the fourth state of the DMAC cycle, the next DMA transfer will
be executed because the sampling is performed at the second state of the DMAC cycle.
Figure 9.20 DREQ Sampling Timing in Cycle-Steal Mode (Output with DREQ Level
Detection and DACK Active-Low) (Dual Address Mode, Bus Cycle = DRAM Bus Cycle
CK
DREQ
Bus cycle
CPU
DACK
Note: When DREQ is negated at the fourth state of the DMAC cycle, the next DMA transfer will
be executed because the sampling is performed at the second state of the DMAC cycle.
Figure 9.21 DREQ Sampling Timing in Cycle-Steal Mode (Output with DREQ Level
Detection and DACK Active-Low) (Single Address Mode, Bus Cycle = Address/Data
Tp Tr Tc
CPU CPU DMAC(R)
(Long Pitch Normal Mode))
T1
CPU CPU
Multiplex I/O Bus Cycle)
Tc Tp Tr
DMAC
CPU DMAC (R)
(W)
DMAC (R): DMAC read cycle
DMAC (W): DMAC write cycle
T2 T3 T4 T1
DMAC CPU
Tc Tc
DMAC
CPU
(W)
T2 T3 T4
DMAC CPU
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