Hitachi SH7032 Hardware Manual page 644

Table A.43 WCR2 Bit Functions
Bit Bit Name
15–8 Single mode
DMA memory
read wait state
control (DRW7–
DRW0)
7–0 Single mode
DMA memory
write wait state
control (DWW7–
DWW0)
WAIT Pin
Value Signal Input
0 Not sampled
during single
mode DMA
memory read
cycle
1 Sampled
during single
mode DMA
memory read
cycle
(Initial value)
0 Not sampled
during single
mode DMA
memory write
cycle
1 Sampled
during single
mode DMA
memory write
cycle
(Initial value)
Description
Number of Single Mode DMA
External Space Cycle States
External DRAM
Memory Space Space
• Areas 1, 3–5, 7:
Column
fixed at 1 cycle
address cycle:
• Areas 0, 2, 6:
Fixed at 1
cycle (short-
1 cycle + long
pitch)
wait state
• Areas 1, 3–5, 7:
Column
wait state is 2
address cycle:
cycles plus
Wait state is 2
WAIT
cycles plus
• Areas 0, 2, 6:
WAIT (long-
pitch)
1 cycle + long
wait state, or
wait state from
WAIT
• Areas 1, 3–5, 7:
Column
fixed at 1 cycle
address cycle:
• Areas 0, 2, 6:
Fixed at 1
cycle (short-
1 cycle + long
pitch)
wait state
• Areas 1, 3–5, 7:
Column
wait state is 2
address cycle:
cycles plus
Wait state is 2
WAIT
cycles plus
• Areas 0, 2, 6:
WAIT (long-
pitch)
1 cycle + long
wait state, or
wait state from
WAIT
Multiplex
I/O
Wait state is 4
cycles plus
WAIT
Wait state is 4
cycles plus
WAIT
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