Tpc Output Mode Register (Tpmr) Tpc - Hitachi SH7032 Hardware Manual

A.2.64 TPC Output Mode Register (TPMR)
• Start Address: H'5FFFFF0
• Bus Width: 8/16
Register Overview:
Bit:
Bit name:
Initial value:
R/W:
Table A.65 TPMR Bit Functions
Bit Bit Name
3 Group 3 non-
overlap (G3NOV)
2 Group 2 non-
overlap (G2NOV)
1 Group 1 non-
overlap (G1NOV)
0 Group 0 non-
overlap (G0NOV)
7 6 5
— — —
1 1 1
— — —
Value Description
0 TPC output group 3 operates normally (the output value is
updated at every compare match A of the selected ITU)
1 TPC output group 3 operates in non-overlap mode (1 output and
0 output can be performed independently upon compare
matches A and B of the selected ITU)
0 TPC output group 2 operates normally (the output value is
updated at every compare match A of the selected ITU)
1 TPC output group 2 operates in non-overlap mode (1 output and
0 output can be performed independently upon compare
matches A and B of the selected ITU)
0 TPC output group 1 operates normally (the output value is
updated at every compare match A of the selected ITU)
1 TPC output group 1 operates in non-overlap mode (1 output and
0 output can be performed independently upon compare
matches A and B of the selected ITU)
0 TPC output group 0 operates normally (the output value is
updated at every compare match A of the selected ITU)
1 TPC output group 0 operates in non-overlap mode (1 output and
0 output can be performed independently upon compare
matches A and B of the selected ITU)
4 3 2
— G3NOV G2NOV G1NOV G0NOV
1 0 0
— R/W R/W
TPC
1 0
0 0
R/W R/W
(Initial value)
(Initial value)
(Initial value)
(Initial value)
635