Hitachi SH7032 Hardware Manual page 686

Table B.2 Pin States in Address Space Accesses (cont)
8-Bit
Pin Name Space
CS7–CS0
Valid
RAS
High
CASH
High
CASL
High
AH
Low
RD
R Low
W High
WRH/LBS
— *
R
— *
W
WRL/WR
R High
W Low
A0/HBS A0
A21–A1 Address Address
AD15–AD8 High-Z
AD7–AD0 Data
DPH High-Z
DPL Parity
R: Read
W: Write
Valid: Chip select signal for the area accessed is low; other chip select signals are high.
Parity: When an area 2 parity check is selected with the parity check enable bits (PCHK1, PCHK0)
in the parity control register (PCR), this pin is used as the parity pin.
Note: * Cannot be used; available only for 16-bit space access.
External Memory Space
WRH, WRL, A0 System
Upper Lower
Byte Byte
Valid Valid
High High
High High
High High
Low Low
Low Low
High High
High High
Low High
High High
High Low
A0 A0
Address
Data High-Z
High-Z Data
Parity High-Z
High-Z Parity
16-Bit Space
WR, HBS, LBS System
Upper
Word Byte
Valid Valid
High High
High High
High High
Low Low
Low Low
High High
High High
Low High
High High
Low Low
A0 Low
Address Address
Data Data
Data High-Z
Parity Parity
Parity High-Z
Lower
Byte Word
Valid Valid
High High
High High
High High
Low Low
Low Low
High High
Low Low
Low Low
High High
Low Low
High Low
Address Address
High-Z Data
Data Data
High-Z Parity
Parity Parity
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