Timer Control Registers 0-4 (Tcr0-Tcr4) Itu - Hitachi SH7032 Hardware Manual

A.2.14 Timer Control Registers 0–4 (TCR0–TCR4)
• Start Address: H'5FFFF04 (channel 0), H'5FFFF0E (channel 1), H'5FFFF18 (channel 2),
H'5FFFF22 (channel 3), H'5FFFF32 (channel 4)
• Bus Width: 8
Register Overview:
Bit:
Bit name:
Initial value:
R/W:
Note: * Undetermined
Table A.15 TCR0–TCR4 Bit Functions
Bit Bit name
6,5 Counter clear 1, 0 (CCLR1,
CCLR0)
4,3 Clock edge 1, 0 (CKEG1,
CKEG0)
2–0 Timer prescaler 2–0
(TPSC2–TPSC0)
Note: * 0 or 1
578
7 6 5
— CCLR1 CCLR0
0 0
*
— R/W R/W
Value
0 0
0 1
1 0
1 1
0 0
0 1
1
*
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
4 3
CKEG1 CKEG0
0 0
R/W R/W
Description
TCNT clear disabled
TCNT cleared upon GRA compare match/input
capture
TCNT cleared upon GRB compare match/input
capture
Synchronized clear. TCNT cleared in
synchronization with counter clear of other timers
operating in sync
Count on rising edge
Count on falling edge
Count on both rising and falling edges
Internal clock: Count on φ
0
Internal clock: Count on φ/2
1
Internal clock: Count on φ/4
0
Internal clock: Count on φ/8
1
0 External clock A: Count on TCLKA pin input
1 External clock B: Count on TCLKB pin input
0 External clock C: Count on TCLKC pin input
1 External clock D: Count on TCLKD pin input
2 1
TPSC2 TPSC1 TPSC0
0 0
R/W R/W
(Initial value)
(Initial value)
(Initial value)
ITU
0
0
R/W