Hitachi SH7032 Hardware Manual page 182

T
CK
A21–A0
RAS
CAS
Control of Insertion of Wait States Using the WAIT Pin Input Signal: The number of wait
states inserted into the DRAM access cycle can be controlled by setting WCR1 and WCR2. When
the corresponding bits in WCR1 and WCR2 are cleared to 0, the column address output cycle ends
in 1 state and no wait states are inserted. When the bit is 1, the WAIT pin input signal is sampled
on the rise of the system clock (CK) directly preceding the second state of the column address
output cycle and the wait state is inserted as long as the level is low. When a high level is detected,
it shifts to the second state. Figure 8.20 shows the wait state timing in a long pitch bus cycle.
T
CK
A21–A0
RAS
CAS
WAIT
Figure 8.20 Wait State Timing during DRAM Access (Long Pitch)
When the RW1 bit is set to 1, the number of wait states selected by CBR refresh wait state
insertion bits 1 and 0 (RLW1, RLW0) in the refresh control register (RCR) are inserted into the
CAS-before-RAS refresh cycle.
1 T 2
p p
Figure 8.19 Precharge Timing (Long Pitch)
T
p r
Row address
T T 1
r c
Row address Column address
T 1 T (wait state)
c cw
Column address
T 2
c
T 2
c
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