Hitachi SH7032 Hardware Manual page 441

Constraints on DMAC Use:
• When using an external clock source for the serial clock, update TDR with the DMAC, and
then input the transmit clock after the elapse of five system clocks or more. If a transmit clock
is input in the first four system clocks after TDR is written, an error may occur (figure 13.22).
• Before reading the receive data register (RDR) with the DMAC, select the receive-data-full
interrupt of the SCI as an activation source using the resource select bit (RS) in the channel
control register (CHCR).
SCK
t
TDRE
Note: During external clock operation, an error may occur if t is 4φ or less.
Figure 13.22 Example of Synchronous Transmitting with DMAC
Cautions on Use of Synchronous External Clock Mode:
• Set TE = RE = 1 only when the external clock SCI is 1.
• Do not set TE = RE = 1 until at least 4 clocks after the external clock SCK has changed from 0
to 1.
• When receiving, RDRF is set to 1 when RE is cleared to 0 2.5–3.5 clocks after the rising edge
of the RxD D7 bit SCK input, but copying to RDR is not possible.
Caution on Synchronous Internal Clock Mode: When receiving, RDRF is set to 1 when RE is
cleared to 0 1.5 clocks after the rising edge of the RxD D7 bit SCK output, but copying to RDR is
not possible.
406
D0 D1 D2 D3 D4 D5 D6 D7