BARH/BARL
Internal address
bits 31–0
CD1
CPU cycle
DMA cycle
ID1
Instruction fetch
Data access
RW1
Read cycle
Write cycle
SZ1
Byte size
Word size
Longword size
BAMRH/BAMRL
32
32
CD0
ID0
RW0
SZ0
Figure 6.2 Break Condition Logic
32
32
32
User
break
interrupt
89