Reset Control/Status Register (Rstcsr) - Hitachi H8S/2378, H8S/2378R Series Hardware Manual

Bit Bit Name
Note: * Only a write of 0 is permitted, to clear the flag.
14.3.3

Reset Control/Status Register (RSTCSR)

RSTCSR controls the generation of the internal reset signal when TCNT overflows, and selects
the type of internal reset signal. RSTCSR is initialized to H'1F by a reset signal from the 5(6 pin,
but not by the WDT internal reset signal caused by overflows.
Bit Bit Name
7 WOVF
6 RSTE
5 —
4 —
to
0
Note: * Only a write of 0 is permitted, to clear the flag.
Initial Value R/W
Initial Value R/W
0 R/(W)*
0 R/W
0 R/W
1 —
Description
111: Clock ø/131072 (frequency: 1.68 s)
Description
Watchdog Timer Overflow Flag
This bit is set when TCNT overflows in watchdog
timer mode. This bit cannot be set in interval
timer mode, and only 0 can be written.
[Setting condition]
Set when TCNT overflows (changed from H'FF to
H'00) in watchdog timer mode
[Clearing condition]
Cleared by reading RSTCSR when WOVF = 1,
and then writing 0 to WOVF
Reset Enable
Specifies whether or not a reset signal is
generated in the chip if TCNT overflows during
watchdog timer operation.
0: Reset signal is not generated even if TCNT
overflows
(Though this LSI is not reset, TCNT and TCSR in
WDT are reset)
1: Reset signal is generated if TCNT overflows
Reserved
Can be read and written, but does not affect
operation.
Reserved
These bits are always read as 1 and cannot be
modified.
Rev. 1.0, 0901, page 617 of 904