Setting User Break Conditions - Hitachi SH7032 Hardware Manual

6.4

Setting User Break Conditions

CPU Instruction Fetch Bus Cycle:
• Register settings: BARH = H'0000, BARL = H'0404, BBR = H'0054
Conditions set: Address = H'00000404, bus cycle = CPU, instruction fetch, read (operand size
not included in conditions)
A user break interrupt will occur immediately before the instruction at address H'00000404. If
the instruction at address H'00000402 can accept an interrupt, the user break exception
handling will be executed after that instruction is executed. The instruction at H'00000404 will
not be executed. The value saved to the PC is H'00000404.
• Register settings: BARH = H'0015, BARL = H'389C, BBR = H'0058
Conditions set: Address = H'0015389C, bus cycle = CPU, instruction fetch, write (operand size
not included in conditions)
No user break interrupt occurs, because no instruction fetch cycle is ever a write cycle.
• Register settings: BARH = H'0003, BARL = H'0147, BBR = H'0054
Conditions set: Address = H'00030147, bus cycle = CPU, instruction fetch, read (operand size
not included in conditions)
No user break interrupt occurs, because instructions are always fetched from even addresses. If
the first fetched address after a branch is odd and a user break is set on this address, however,
user break exception handling will be carried out after address error exception handling.
CPU Data Access Bus Cycle:
• Register settings: BARH = H'0012, BARL = H'3456, BBR = H'006A
Conditions set: Address = H'00123456, bus cycle = CPU, data access, write, word
A user break interrupt occurs when word data is written to address H'00123456.
• Register settings: BARH = H'00A8, BARL = H'0391, BBR = H'0066
Conditions set: Address = H'00A80391, bus cycle = CPU, data access, read, word
No user break interrupt occurs, because word data access is always to an even address.
DMA Cycle:
• Register setting: BARH = H'0076, BARL = H'BCDC, BBR = H'00A7
Conditions set: Address = H'0076BCDC, bus cycle = DMA, data access, read, longword
A user break interrupt occurs when longword data is read from address H'0076BCDC.
• Register setting: BARH = H'0023, BARL = H'45C8, BBR = H'0094
Conditions set: Address = H'002345C8, bus cycle = DMA, instruction fetch, read (operand size
not included)
No user break interrupt occurs, because a DMA cycle includes no instruction fetch.
91