Hitachi SH7032 Hardware Manual page 574

CK
A21–A0
RAS
CAS
RD(Read)
WRH, WRL,
WR(Read)
AD15–AD0
DPH, DPL
(Read)
DACK0
DACK1
(Read)
RD(Write)
WRH, WRL,
WR(Write)
AD15–AD0
(Write)
DPH, DPL
(Write)
DACK0
DACK1
(Write)
Notes: *1 For t
CAC2
*2 For t
ACC2
*3 For t
RAC2
is measured from A21–A0, CAS, or RAS, whichever is negated first.
*4 t
RDH
Figure 20.57 DRAM Bus Cycle: (Long-Pitch, Normal Mode)
T
p
t
AD
t
RASD1
t
RAC2
× (n + 1) – 25 instead of t
, use t
cyc
× (n + 2) – 30 instead of t
, use t
cyc
× (n + 2.5) – 20 instead of t
, use t
cyc
T T
r c1
t
AD
Row
t
RAH
t
RDD
t
CAC2
*2
t
ACC2
*3
t
DACD1
t
WSD1
t
WDD1
t
WPDD1
t
DACD3
× (n + 1) – t
cyc
× (n + 2) – t
cyc
× (n + 2.5) – t
cyc
T
c2
Column
t
DS
t
CASD2
t
RSD
t
WCH
*1
t
RDS
t
DACD2
t
WSD2
t
WDH
t
WPDH
t
DACD3
– t .
CASD2 RDS
– t .
AD RDS
– t
RASD1 RDS
t
RASD2
t
CASD3
*4
t
RDH
.
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