Port A Data Register (Padr) - Hitachi SH7032 Hardware Manual

Table 16.1 Port A Register
Name
Port A data register
Note: * Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9 are ignored. For
details on the register addresses, see section 8.3.5, Area Descriptions.
16.2.2

Port A Data Register (PADR)

PADR is a 16-bit read/write register that stores data for port A. Bits PA15DR–PA0DR correspond
to the PA15/IRQ3/DREQ1–PA0/CS4/TIOCA0 pins. When the pins are used as ordinary outputs,
they will output whatever value is written in PADR; when PADR is read, the register value will be
output regardless of the pin status. When the pins are used as ordinary inputs, the pin status rather
than the register value is read directly when PADR is read. When a value is written to PADR, that
value can be written into PADR, but it will not affect the pin status. Table 16.2 shows port A data
register read/write operations.
PADR is initialized by a power-on reset. However, PADR is not initialized by a manual reset, or
in standby mode or sleep mode.
Bit:
Bit name: PA15DR PA14DR PA13DR PA12DR PA11DR PA10DR PA9DR PA8DR
Initial value:
R/W:
Bit:
Bit name:
Initial value:
R/W:
Table 16.2 Port A Data Register (PADR) Read/Write Operations
PAIOR Pin Status
0 Input
Other function
1 Output
Other function
442
Abbreviation R/W
PADR R/W
15 14
0 0
R/W R/W
7 6
PA7DR PA6DR PA5DR
0 0
R/W R/W
Read
Pin status
Pin status
PADR value
PADR value
Initial Value
H'0000
13 12 11
0 0
R/W R/W R/W
5 4
PA4DR PA3DR
0 0
R/W R/W R/W
Write
Can write to PADR, but it has no effect on pin
status.
Can write to PADR, but it has no effect on pin
status.
Value written is output by pin
Can write to PADR, but it has no effect on pin
status.
Address* Access Size
H'5FFFFC0 8, 16, 32
10 9
0 0 0
R/W R/W
3 2 1
PA2DR PA1DR PA0DR
0 0 0
R/W R/W
8
0
R/W
0
0
R/W