Hitachi SH7032 Hardware Manual page 151

Bit 12: BE
0
1
• Bit 11 (CAS Duty (CDTY)): CDTY selects 35% or 50% of the TC state as the high-level duty
ratio of the signal CAS in short-pitch access. When cleared to 0, the CAS signal high level
duty is 50%; when set to 1, it is 35%.
Bit 11: CDTY
0
1
• Bit 10 (Multiplex Enable Bit (MXE)): MXE determines whether or not DRAM row and
column addresses are multiplexed. When cleared to 0, addresses are not multiplexed; when set
to 1, they are multiplexed.
Bit 10: MXE
0
1
• Bits 9 and 8 (Multiplex Shift Count 1 and 0 (MXC1 and MXC0)): Shift row addresses
downward by a certain number of bits (8–10) when row and column addresses are multiplexed
(MXE = 1). Regardless of the MXE bit setting, these bits also select the range of row addresses
compared in burst operation.
Bit 9: Bit 8:
MXC1 MXC0
0 0
1
1 0
1
• Bits 7–0 (Reserved): These bits are always read as 0. The write value should always be 0.
116
Description
Normal mode: full access
Burst operation: high-speed page mode
Description
CAS signal high level duty cycle is 50% of the T
CAS signal high level duty cycle is 35% of the T
Description
Multiplexing of row and column addresses disabled
Multiplexing of row and column addresses enabled
Row Address Shift
(MXE = 1)
8 bits (Initial value)
9 bits
10 bits
Reserved
Row Address Bits Compared
(in Burst Operation) (MXE = 0 or 1)
A8–A27
A9–A27
A10–A27
Reserved
(Initial value)
state (Initial value)
C
state
C
(Initial value)
(Initial value)