Hitachi SH7032 Hardware Manual page 567

Table 20.20 Bus Timing (2) (cont)
Conditions: V = 3.3 V ±0.3V, AV
CC
AV , V
CC
Note: * Regular-specification products; for wide-temperature-range products, Ta = –40 to +85°C
Item
AH delay time 1
AH delay time 2
Multiplexed address delay time t
Multiplexed address hold time
DACK0, DACK1 delay time 1
DACK0, DACK1 delay time 2
DACK0, DACK1 delay time 3 *
DACK0, DACK1 delay time 4
DACK0, DACK1 delay time 5
35% duty *
Read delay time
50% duty
Data setup time for CAS
CAS setup time for RAS
Row address hold time
Write command hold time
35% duty *
Write command
setup time
50% duty
Access time from CAS
4
precharge *
Notes: *1 When frequency is 10 MHz or more.
*2 n is the number of wait cycles.
*3 –5ns for parity output of DRAM long-pitch access.
*4 If the access time is satisfied, t
*5 In the relationship between t
exist in the logical structure.
532
= 3.3 V ±0.3V, AV
CC
= 0 V, φ = 12.5 MHz, Ta = –20 to +75°C *
= AV
SS SS
Symbol
t
AHD1
t
AHD2
MAD
t
MAH
t
DACD1
t
DACD2
5
t
DACD3
t
DACD4
t
DACD5
1
t
RDD
t
DS
t
CSR
t
RAH
t
WCH
1
t
WCS
t
ACP
RDS
CASD2
= V
CC
Min Max
— 40
— 40
— 40
–10 —
— 40
— 40
— 40
— 40
— 40
× 0.35 + 35
— t
cyc
× 0.5 + 35
— t
cyc
3
0 *
—
10 —
10 —
15 —
0 —
0 —
t —
cyc
−20
need not be satisfied.
and t for t
CASD3 DACD3
±0.3V, AV = 3.0 V to
CC ref
Unit Figures
ns 20.63
ns
ns
ns
ns 20.52, 20.53, 20.55–
20.58, 20.63, 20.64
ns
ns 20.53, 20.57, 20.58,
20.63
ns 20.55, 20.56
ns
ns 20.52, 20.53, 20.55–
20.59, 20.63
ns
ns 20.55, 20.57
ns 20.60–20.62
ns 20.55, 20.57
ns
ns 20.55
ns
ns 20.56
, the pair of Min-Max is not