Wait State Control Register 2 (Wcr2) Bsc - Hitachi SH7032 Hardware Manual

Table A.42 Bit Functions (cont)
Bit Bit Name
1 Write wait
state control
(WW1)
Note: * During a CBR refresh, the WAIT signal is ignored and the wait state inserted using the
RLW1 and RLW0 bits.
A.2.42 Wait State Control Register 2 (WCR2)
• Start Address: H'5FFFFA4
• Bus Width: 8/16/32
Register Overview:
Bit:
Bit name:
Initial value:
R/W:
Bit:
Bit name:
Initial value:
R/W:
608
DRAM Space
Value (BCRDRAME = 1)
0 Column address cycle: 1 cycle
(short-pitch)
1 Column address cycle: Wait state
is 2 cycles + WAIT (long-pitch)
(Initial value)
15 14
DRW7 DRW6 DRW5
1 1
R/W R/W
7 6
DWW7 DWW6 DWW5
1 1
R/W R/W
Description
13 12 11
DRW4 DRW3
1 1
R/W R/W R/W
5 4
DWW4 DWW3
1 1
R/W R/W R/W
Area 1 External Memory Space
(BCRDRAME = 1)
Setting prohibited
Wait state is 2 cycles + WAIT
10 9
DRW2 DRW1
1 1 1
R/W R/W
3 2 1
DWW2 DWW1
1 1 1
R/W R/W
BSC
8
DRW0
1
R/W
0
DWW0
1
R/W