Hitachi SH7032 Hardware Manual page 564

Table 20.20 Bus Timing (1) (cont)
Conditions: V = 3.3 V ±0.3V, AV
CC
AV , V
CC
Notes: *1 ROMless products
*2 Regular-specification products; for wide-temperature-range products, Ta = –40 to
+85°C
Item
AH delay time 1
AH delay time 2
Multiplexed address delay time t
Multiplexed address hold time
DACK0, DACK1 delay time 1
DACK0, DACK1 delay time 2
DACK0, DACK1 delay time 3 *
DACK0, DACK1 delay time 4
DACK0, DACK1 delay time 5
35% duty *
Read delay time
50% duty
Data setup time for CAS
CAS setup time for RAS
Row address hold time
Write command hold time
35% duty *
Write command
setup time
50% duty
Access time from
CAS precharge * 6
Notes: *1 HBS and LBS signals are 25 ns.
*2 When frequency is 10 MHz or more.
*3 n is the number of wait cycles.
*4 Access time from addresses A0 to A21 is tcyc-25 ns.
*5 –5ns for parity output of DRAM long-pitch access.
*6 It is not necessary to meet the t
specification is met.
*7 In the relationship of t
does not occur because of the logic structure.
= 3.3 V ±0.3V, AV
CC
= 0 V, φ = 20 MHz *
= AV
SS SS
Symbol
t
AHD1
t
AHD2
MAD
t
MAH
t
DACD1
t
DACD2
7
t
DACD3
t
DACD4
t
DACD5
2
t
RDD
t
DS
t
CSR
t
RAH
t
WCH
2
t
WCS
t
WCS
t
ACP
RDS
and t
CASD2
= V
CC
1
, Ta = –20 to +75°C *
Min Max
— 20
— 20
— 30
0 —
— 23
— 23
— 20
— 20
— 20
× 0.35 + 12
— t
cyc
× 0.5 + 15
— t
cyc
5
0 *
—
10 —
10 —
15 —
0 —
0 —
t —
cyc
−20
specification as long as the access time
with respect to t
CASD3
±0.3V, AV = 3.0 V to
CC ref
2
Unit Figures
ns 20.63
ns
ns
ns
ns 20.52, 20.53, 20.55–
20.58, 20.63, 20.64
ns
ns 20.53, 20.57, 20.58,
20.63
ns 20.55, 20.56
ns
ns 20.52, 20.53, 20.55–
20.59, 20.63
ns
ns 20.55, 20.57
ns 20.60–20.62
ns 20.55, 20.57
ns
ns 20.55
ns
ns 20.56
, a Min-Max combination
DACD3
529