Hitachi SH7032 Hardware Manual page 627

Table A.28 CHCR0–CHCR3 Bit Functions
Bit Bit name
15,14 Destination address
mode bits 1, 0 (DM1,
DM0)
13,12 Source address mode 0 0
bits 1, 0 (SM1, SM0)
11–8 Resource select bits
3–0 (RS3–RS0)
592
Value Description
0 0 Destination address is fixed
0 1 Destination address incremented (+1 for byte transfer;
+2 for word transfer)
1 0 Destination address decremented (–1 for byte
transfer; –2 for word transfer)
1 1 Reserved (cannot be set)
Source address is fixed
0 1 Source address incremented (+1 for byte transfer;
+2 for word transfer)
1 0 Source address decremented (–1 for byte transfer;
–2 for word transfer)
1 1 Reserved (cannot be set)
0 0 0 0 DREQ (external request *
(Dual address mode)
0 0 0 1 Reserved (cannot be set)
0 0 1 0 DREQ (external request *
0 0 1 1 DREQ (external request *
0 1 0 0 RXIO (transfer request by receive-data-full interrupt of
on-chip SCI0) *
0 1 0 1 TXIO (transfer request by transmit-data-empty
interrupt of on-chip SCI0) *
0 1 1 0 RXI1 (transfer request by receive-data-full interrupt of
on-chip SCI1) *
0 1 1 1 TXI1 (transfer request by transmit-data-empty
interrupt of on-chip SCI1) *
1 0 0 0 IMIA0 (input capture A/compare match A interrupt
request of on-chip ITU0) *
1 0 0 1 IMIA1 (input capture A/compare match A interrupt
request of on-chip ITU1) *
1 0 1 0 IMIA2 (input capture A/compare match A interrupt
request of on-chip ITU2) *
1
)
1
) (Single address mode *
1
) (Single address mode *
4
4
4
4
4
4
4
(Initial value)
(Initial value)
(Initial value)
2
)
3
)