Hitachi SH7032 Hardware Manual page 680

Table A.78 Register Status in Reset and Power-Down States (cont)
Category
A/D converter
Pin function controller
(PFC)
Parallel I/O ports (I/O)
Power-down-state related
Note: *3 Bits 15–8 are always undetermined, bits 7–0 always reflect the state of the
corresponding pin.
Abbreviation Power On
ADDRA– Initialized
ADDRD
ADCSR
ADCR
PAIOR,PBIOR Initialized
PACR1,PACR2,
PBCR1,PBCR2
CASCR
PADR,PBDR Initialized
3
*
PCDR
SBYCR Initialized
Reset State
Manual
Initialized
Held
Held
3
*
Initialized
Power-Down State
Standby Sleep
Initialized Held
Held Held
Held Held
3 3
* *
Held Held
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