Contention Between General Register Read And Input Capture - Hitachi SH7032 Hardware Manual

10.6.6

Contention between General Register Read and Input Capture

If an input capture signal is generated during the T3 state of a general register read cycle, the value
before input capture is read. The timing is shown in figure 10.63.
Internal read
Input capture
Figure 10.63 Contention between General Register Read and Input Capture
T1
CK
Address
signal
signal
GR
Internal
data bus
GR read cycle
T2 T3
GR address
X
X
M
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