Hitachi SH7032 Hardware Manual page 312

TCNT4
T
T – 1
H' 0000
H' FFFF
Figure 10.40 Caution on Changing GR Settings with Buffer Operation (2)
When GR Settings are Outside the Count Range (H'0000–GRA3): Waveforms with a duty
cycle of 0% and 100% can be output by setting GR outside the count area. Be sure to make the
direction of the count (increment/decrement) when writing a setting from outside the count area
into the buffer register (BR) the same as the count direction when writing the setting that returns to
within the count area in BR.
GRA3
GR
H' 0000
Output pin
Output pin
BR
GR
Write on decrement
Figure 10.41 Example of Changing GR Settings with Buffer Operation (2)
The above settings are made by detecting the occurrence of a GRA3 compare match or underflow
of TCNT4 and then writing to BR. They can also be accomplished by starting the DMAC with a
GRA3 compare match.
TCNT3
0% duty
Write on increment
Changes prohibited
100% duty
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