Hitachi SH7032 Hardware Manual page 74

Table 2.15 Shift Instructions
Instruction Instruction Code
ROTL Rn 0100nnnn00000100
ROTR Rn 0100nnnn00000101
ROTCL Rn 0100nnnn00100100
ROTCR Rn 0100nnnn00100101
SHAL Rn 0100nnnn00100000
SHAR Rn 0100nnnn00100001
SHLL Rn 0100nnnn00000000
SHLR Rn 0100nnnn00000001
SHLL2 Rn 0100nnnn00001000
SHLR2 Rn 0100nnnn00001001
SHLL8 Rn 0100nnnn00011000
SHLR8 Rn 0100nnnn00011001
SHLL16 Rn 0100nnnn00101000
SHLR16 Rn 0100nnnn00101001
Table 2.16 Branch Instructions
Instruction Instruction Code
BF label 10001011dddddddd
BT label 10001001dddddddd
BRA label 1010dddddddddddd
BSR label 1011dddddddddddd
JMP @Rm 0100mmmm00101011
JSR @Rm 0100mmmm00001011
RTS 0000000000001011
Note: * The execution state is three cycles when program branches, and one cycle when program
does not branch.
Operation
T ← Rn ← MSB
LSB → Rn → T
T ← Rn ← T
T → Rn → T
T ← Rn ← 0
MSB → Rn → T
T ← Rn ← 0
0 → Rn → T
Rn<<2 → Rn
Rn>>2 → Rn
Rn<<8 → Rn
Rn>>8 → Rn
Rn<<16 → Rn
Rn>>16 → Rn
Operation
If T = 0, disp × 2 + PC → PC; if T = 1,
nop
If T = 1, disp × 2 + PC → PC; if T = 0,
nop
Delayed branch, disp × 2 + PC → PC
Delayed branch, PC → PR, disp × 2 +
PC → PC
Delayed branch, Rm → PC
Delayed branch, PC → PR, Rm → PC
Delayed branch, PR → PC
Execution Cycles
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Execution
Cycles
3/1 *
3/1 *
2
2
2
2
2
T Bit
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
—
—
—
—
—
—
T Bit
—
—
—
—
—
—
—
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