Buffer Registers A And B (Bra, Brb) - Hitachi SH7032 Hardware Manual

10.2.8

Buffer Registers A and B (BRA, BRB)

Each buffer register is a 16-bit read/write register that is used in buffer mode. The ITU has four
buffer registers, two each for channels 3 and 4. Buffer operation can be set independently by the
timer function control register (TFCR) bits BFB4, BFA4, BFB3, and BFB3. The buffer registers
are paired with the general registers and their function changes automatically to match the function
of corresponding general register.
The buffer registers are connected to the CPU by a 16-bit bus, so they can be written or read by
either word or byte access. Buffer registers are initialized to H'FFFF by a reset and in standby
mode.
Table 10.6 Buffer Registers A and B (BRA, BRB)
Channel Abbreviation
3 BRA3, BRB3
4 BRA4, BRB4
Bit:
Bit name:
Initial value:
R/W:
Bit:
Bit name:
Initial value:
R/W:
Function
When used for buffer operation:
When the corresponding GRA and GRB are output compare
registers, the buffer registers function as output compare buffer
registers that can automatically transfer the BRA and BRB values to
GRA and GRB upon a compare match.
When the corresponding GRA and GRB are input capture registers,
the buffer registers function as input capture buffer registers that can
automatically transfer the values stored until an input capture in the
GRA and GRB to the BRA and BRB.
15 14 13
1 1
R/W R/W R/W
7 6
1 1
R/W R/W R/W
12 11
1 1 1
R/W R/W
5 4 3
1 1 1
R/W R/W
10 9
1 1
R/W R/W R/W
2 1
1 1
R/W R/W R/W
8
1
0
1
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