Register Configuration - Hitachi SH7032 Hardware Manual

8.1.4

Register Configuration

The BSC has ten registers (listed in table 8.2) which control space division, wait states, DRAM
interface, and parity check.
Table 8.2 Register Configuration
Name
Bus control register
Wait state control register 1
Wait state control register 2
Wait state control register 3
DRAM area control register
Parity control register
Refresh control register
Refresh timer control/status
register
Refresh timer counter
Refresh time constant
register
Notes: *1 Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9 are ignored. For
details on the register addresses, see section 8.3.5, Area Descriptions.
*2 Write only with word transfer instructions. See section 8.2.11, Notes on Register
Access, for details on writing.
104
Abbr. R/W Initial Value
BCR R/W H'0000
WCR1 R/W H'FFFF
WCR2 R/W H'FFFF
WCR3 R/W H'F800
DCR R/W H'0000
PCR R/W H'0000
RCR R/W H'0000
RTCSR R/W H'0000
RTCNT R/W H'0000
RTCOR R/W H'00FF
1
Address *
Bus width
H'5FFFFA0 8,16,32
H'5FFFFA2 8,16,32
H'5FFFFA4 8,16,32
H'5FFFFA6 8,16,32
H'5FFFFA8 8,16,32
H'5FFFFAA 8,16,32
8,16,32 *
H'5FFFFAC
8,16,32 *
H'5FFFFAE
8,16,32 *
H'5FFFFB0
8,16,32 *
H'5FFFFB2
2
2
2
2