Register Configuration - Hitachi SH7032 Hardware Manual

10.1.4

Register Configuration

Table 10.3 summarizes the ITU register configuration.
Table 10.3 Register Configuration
Channel Name
Shared Timer start register
Timer synchro register
Timer mode register
Timer function control register
Timer output control register
0 Timer control register 0
Timer I/O control register 0
Timer interrupt enable register 0 TIER0
Timer status register 0
Timer counter 0
General register A0
General register B0
1 Timer control register 1
Timer I/O control register 1
Timer interrupt enable register 1 TIER1
Timer status register 1
Timer counter 1
General register A1
General register B1
228
Abbrevi- Initial
ation R/W Value
TSTR R/W H'E0/H'60 H'5FFFF00
TSNC R/W H'E0/H'60 H'5FFFF01
TMDR R/W H'80/H'00 H'5FFFF02
TFCR R/W H'C0/H'40 H'5FFFF03
TOCR R/W H'FF/H'7F H'5FFFF31
TCR0 R/W H'80/H'00 H'5FFFF04
TIOR0 R/W H'88/H'08 H'5FFFF05
R/W H'F8/H'78 H'5FFFF06
2
R/(W) *
TSR0 H'F8/H'78 H'5FFFF07
TCNT0 R/W H'00
GRA0 R/W H'FF
GRB0 R/W H'FF
TCR1 R/W H'80/H'00 H'5FFFF0E
TIOR1 R/W H'88/H'08 H'5FFFF0F
R/W H'F8/H'78 H'5FFFF10
2
R/(W) *
TSR1 H'F8/H'78 H'5FFFF11
TCNT1 R/W H'00
GRA1 R/W H'FF
GRB1 R/W H'FF
Access
1
Address *
Size
8
8
8
8
8
8
8
8
8
H'5FFFF08 8, 16, 32
H'5FFFF09 8, 16, 32
H'5FFFF0A 8, 16, 32
H'5FFFF0B 8, 16, 32
H'5FFFF0C 8, 16
H'5FFFF0D 8, 16
8
8
8
8
H'5FFFF12 8, 16
H'5FFFF13 8, 16
H'5FFFF14 8, 16, 32
H'5FFFF15 8, 16, 32
H'5FFFF16 8, 16, 32
H'5FFFF17 8, 16, 32