Register Descriptions; Receive Shift Register; Receive Data Register - Hitachi SH7032 Hardware Manual

Table 13.2 Registers
Address *
Channel
0 H'05FFFEC0
H'05FFFEC1
H'05FFFEC2
H'05FFFEC3
H'05FFFEC4
H'05FFFEC5
1 H'05FFFEC8
H'05FFFEC9
H'05FFFECA
H'05FFFECB
H'05FFFECC Serial status register
H'05FFFECD Receive data register
Notes: *1 Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9 are ignored. For
details on the register addresses, see section 8.3.5, Area Descriptions.
*2 Only 0 can be written, to clear flags.
13.2

Register Descriptions

13.2.1

Receive Shift Register

The receive shift register (RSR) receives serial data. Data input at the RxD pin is loaded into RSR
in the order received, LSB (bit 0) first. In this way the SCI converts received data to parallel form.
When one byte has been received, it is automatically transferred to the receive data register
(RDR). The CPU cannot read or write to RSR directly.
Bit:
Bit name:
R/W:
13.2.2

Receive Data Register

The receive data register (RDR) stores serial receive data. The SCI completes the reception of one
byte of serial data by moving the received data from the receive shift register (RSR) into RDR for
storage. RSR is then ready to receive the next data. This double buffering allows the SCI to
receive data continuously.
352
1
Name
Serial mode register
Bit rate register
Serial control register
Transmit data register TDR0
Serial status register
Receive data register
Serial mode register
Bit rate register
Serial control register
Transmit data register TDR1
7 6
— —
Abbreviation
SMR0
BRR0
SCR0
SSR0
RDR0
SMR1
BRR1
SCR1
SSR1
RDR1
5 4 3
— — —
Initial Access
R/W Value size
R/W H'00 8, 16
R/W H'FF 8, 16
R/W H'00 8, 16
R/W H'FF 8, 16
2
R/(W) *
H'84 8, 16
R H'00 8, 16
R/W H'00 8, 16
R/W H'FF 8, 16
R/W H'00 8, 16
R/W H'FF 8, 16
2
R/(W) *
H'84 8, 16
R H'00 8, 16
2 1
— —
0
—