Hitachi SH7032 Hardware Manual page 224

Initial settings
(SAR, DAR, TCR, CHCR, DMAOR)
DE, DME = 1 and
NMIF, AE, TE = 0?
Transfer request
Transfer (1 transfer unit); TCR–1
→ TCR, SAR and DAR updated
DEI interrupt request
(when IE = 1)
No
NMIF = 1, AE = 1,
DE = 0, and DME
Normal end Transfer ends
Notes: *1 In auto-request mode, transfer begins when NMIF, AE, and TE are all 0 and the DE
and DME bits are set to 1.
*2 DREQ = level detection in burst mode (external request), or cycle steal mode.
*3 DREQ = edge detection in burst mode (external request), or auto request mode in
burst mode.
Start
No
Yes
No
*1
occurs?
Yes
No
TCR = 0?
Yes
Does
= 0?
Yes
Figure 9.2 DMA Transfer Flowchart
transfer request mode,
DREQ detection selection
*3
Does
NMIF = 1, AE = 1,
DE = 0, or DME
= 0?
Yes
Transfer aborted
*2
Bus mode,
system
No
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