Bit Rate Register (Brr) - Hitachi SH7032 Hardware Manual

• Bit 0 (Multiprocessor Bit Transfer (MPBT)): MPBT stores the value of the multiprocessor bit
added to transmit data when a multiprocessor format is selected for transmitting in
asynchronous mode. The MPBT setting is ignored in synchronous mode, when a
multiprocessor format is not selected, or when the SCI is not transmitting.
Bit 0: MPBT Description
0 Multiprocessor bit value in transmit data is 0
1 Multiprocessor bit value in transmit data is 1
13.2.8

Bit Rate Register (BRR)

The bit rate register (BRR) is an eight-bit register that, together with the baud rate generator clock
source selected by the CKS1 and CKS0 bits in the serial mode register (SMR), determines the
serial transmit/receive bit rate.
The CPU can always read and write to BRR. BRR is initialized to H'FF by a reset and in standby
mode. SCI0 and SCI1 have independent baud rate generator control, so different values can be set
in the two channels.
Bit:
Bit name:
Initial value:
R/W:
Table 13.3 shows examples of BRR settings in asynchronous mode; table 13.4 shows examples of
BBR settings in synchronous mode.
7 6
1 1
R/W R/W R/W
5 4 3
1 1 1
R/W R/W
(Initial value)
2 1
1 1
R/W R/W R/W
0
1
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