Reset Control/Status Register (Rstcsr) - Hitachi H8/3035 Series Hardware Manual

10.2.3 Reset Control/Status Register (RSTCSR)

Bit 7
WRST
Initial value 0
Read/Write R/(W)
Watchdog timer reset
Indicates that a reset signal has been generated
RSTCSR is an 8-bit readable and writable
generated by watchdog timer overflow, and controls external output of the reset signal.
Bits 7 and 6 are initialized by input of a reset signal at the
reset signals generated by watchdog timer overflow.
Notes: 1. RSTCSR is write-protected by a password. For details see section 10.2.4, Notes on
Register Access.
2. Only 0 can be written in bit 7, to clear the flag.
Bit 7—Watchdog Timer Reset (WRST): During watchdog timer operation, this bit indicates
that TCNT has overflowed and generated a reset signal. This reset signal resets the entire this
chip internally. If bit RSTOE is set to 1, this reset signal is also output (low) at the
initialize external system devices.
Bit 7
WRST Description
0 [Clearing condition]
Cleared by reset signal input at
when WRST = 1, then writing 0 in WRST
1 [Setting condition]
Set when TCNT overflow generates a reset signal during watchdog timer operation
282
6 5
RSTOE —
0 1
* 2
R/W —
Reset output enable
Enables or disables external output of the reset signal
register that indicates when a reset signal has been
*1
5(6
4 3 2
— — —
1 1 1
— — —
Reserved bits
5(6
pin. They are not initialized by
pin, or cleared by reading WRST (Initial value)
1 0
— —
1 1
— —
5(62
pin to